A 23.4 mW −72-dBc Reference Spur 40 GHz CMOS PLL Featuring a Spur-Compensation Phase Detector

This letter introduces a novel phase detector (PD) for suppressing the reference spur in 40 GHz integer- $N$ phase-locked loop (PLL). Coined as spur-compensation (SCPD), proposed SCPD duplicates itself to an auxiliary path edge-combined alignment, such that spurs generated by two paths mutually compensate each other, achieving net effect of canceling. Implemented 40-nm CMOS technology, PLL shows less than −71.4-dBc spur, −98- and −117-dBc/Hz noise at 1- 10-MHz offset, respectively, minimum rms jitter 114 fs (10 k–100 MHz). It consumes 23.4-mW power from 1.1-V supply, leading figure merit (FoM) −245 dB.